NTE7098
Integrated Circuit Current Mode Pulse Width Modulator (PWM) Control Circuit 8-PIN DIP

See also >>> NTE7099

Description:
The NTE7098 and NTE7099 are integrated circuits in 8-Lead DIP type packages that incorporate a new precision temperature-controlled oscillator to minimize variations in frequency. An internal toggle flip-flop, which blanks the output off every other clock cycle, limits the duty-cycle range to less than 50%. An under-voltage lockout ensures that VREF is stabilized before the output stage is enabled. Other features include low start-up current, pulse-by-current limiting, and high-current totem pole output for driving capacitive loads, such as the gate of a power MOSFET. The output is low in the off state, consistent with N-channel devices.

Features:
- Optimized for Off-Line Control
- Temperature Compensated Oscillator
- 50% Maximum Duty-Cycle Clamp
- Vref Stabilized before Output Stage is Enabled
- Low Start-Up Current
- Pulse-by Pulse Current Limiting
- Improved U/V Lockout
- Double Pulse Suppression
- 1% Trimmed Bandgap Reference
- High Current Totem Pole Output

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Absolute Maximum Ratings:
Supply Voltage (ICC < 30mA).................................................Self Limiting
Supply Voltage (Low Impedence Source).............................................. 30V
Output Current.....................................................................±1A
Output Energy (Capacitive Load).....................................................5μJ
Analog Inputs (VFB, VSENSE).................................................-0.3V to VCC
Error Amp Output Sink Current.....................................................10mA

Electrical Characteristics: (0° </= T_A </= +70°C, V_CC = +15V, R_t = 10k, C_t = 3.3nF for sawtooth mode, Note 1 unless otherwise specified)

Parameter	Test Conditions	Min	Typ	Max	Unit
Reference Section
Output Voltage	TJ = +25°C, Iref = 1mA	4.9	5.0	5.1	V
Line Regulation	12V </= VIN </= 25V	-	6	20	mV
Load Regulation	1mA </= Iref </= 20mA	-	6	25	mV
Temperature Stability	Note 2	-	0.2	0.4	mV/°C
Total Output Variation	Line, Load, Temperature, Note 2	4.82	-	5.18	V
Output Noise Voltage	10Hz </= f </= 10kHz, TJ = +25°C, Note 2	-	50	-	µV
Long Term Stability	TA = +125°C, 1000Hrs., Note 2	-	5	25	mV
Output Short Circuit	TA = +25°C	-30	-100	-180	mA
Oscillator Section
Initial Accuracy	Sawtooth Mode, TJ = +25°C	47	52	57	kHz
Voltage Stability	12V </= VCC </= 25V	-	0.2	1.0	%
Temperature Stability	Sawtooth Mode, 0° </= TA </= +70°C, Note 2	-	5	-	%
Amplitude	VPIN4 peak to peak	-	1.7	-	V
Error Amp Section
Input Voltage	VCOMP = 2.5V	2.42	2.50	2.58	V
Input Bias Current	VFB = 0V	-	-0.3	-2.0	µA
AVOL	2V </= VO </= 4V	65	90	-	dB
Unity Gain Bandwidth	Note 2	0.7	1.0	-	MHz
PSRR	12V </= VCC </= 25V	60	70	-	dB
Output Sink Current	VFB = 2.7V, VCOMP = 1.1V	2	6	-	mA
Output Source Current	VFB = 2.3V, VCOMP = 5V	-0.5	-0.8	-	mA
VOUT High	VFB = 2.3V, RL = 15k to GND	5	6	-	V
VOUT Low	VFB = 2.7V, RL = 15k to Pin8	-	0.7	1.1	V
Current Sense Section
Gain	Note 3, Note 4	2.85	3.00	3.15	V/V
Maximum Input Signal	VCOMP = 5V, Note 3	0.9	1.0	1.1	V
PSRR	12V </= VCC </= 25V, Note 3	-	70	-	dB
Input Bias Current		-	-2	-10	µA
Delay to Output	TJ = +25°C, Note 2	-	150	300	ns
Output Section
Output Low Level	ISINK = 20mA	-	0.1	0.4	V
	ISINK = 200mA	-	1.5	2.2	V
Output High Level	ISOURCE = 20mA	13.0	13.5	-	V
	ISOURCE = 200mA	12.0	13.5	-	V
Rise Time	TJ = +25°C, CL = 1nF, Note 2	-	50	150	ns
Fall Time	TJ = +25°C, CL = 1nF, Note 2	-	50	150	ns
Total Standby Current
Start-Up Current		-	0.5	1.0	mA
Operating Supply Current	VFB = VSENSE = 0V, RT = 10k, CT = 3.3nF	-	11	17	mA
VCC Zener Voltage	ICC = 25mA	-	34	-	V
PWM Section
Maximum Duty Cycle		46	48	50	%
Minimum Duty Cycle		-	-	0	%
Under-Voltage Lockout Section
Start Threshold       NTE7098       NTE7099		14.5 7.8	16.0 8.4	17.5 9.0	V V
Minimum Operating Voltage       NTE7098       NTE7099	After Turn-On	8.5 7.0	10.0 7.9	11.5 8.2	V V

Note 1.	Adjust VCC above the start threshold before setting at 15V.
Note 2.	These parameters, although guaranteed, are not 100% tested in production.
Note 3.	Parameter measured at trip point of latch with VPIN2 = 0.
Note 4.	Gain defined as: A = VCOMP / VSENSE; 0 </= VPin3 </= 0.8V.

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