NTE2114 NTE-2114 | ECG2114 ECG-2114 | NTE Electronics
NTE2114
Integrated Circuit
MOS, Static 4K RAM, 300ns
Description:
The NTE2114 1024-word 4-bit static random access memory is fabricated using N-channel silicon-
gate technology. All internal circuits are fully static and therefore require no clocks or refreshing for
operation. The data is read out nondestructively and has the same polarity as the input data. Common
input/output pins are provided.
The separate chip select input (CS) allows easy memory expansion by OR-tying individual devices
to a data bus.
Features:
- All Inputs and Outputs Directly TTL Compatible
- Static Operation: No Clocks or Refreshing Required
- Low Power: 225mW Typ
- High Speed: Down to 300ns Access Time
- TRI-STATE Output for Bus interface
- Common Data In and Data Out Pins
- Single 5V Supply
- Standard 18-Lead DIP Package
Info as pdf-file
NTE-ECG replacement list as pdf-file
NTE-ECG diagrams
Absolute Maximum Ratings:
Voltage at Any Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
Power Dissipation, PD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65° to +150°C
Lead Temperature (During Soldering, 10sec), TL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C
Functional Description:
Two pins control the operation of the NTE2114. Chip Select (CS) enables write and read operations
and controls TRI-STATING of the data-output buffer. Write Enable (WE) chooses between READ
and WRITE modes and also controls output TRI-STATING. The truth table details the states produced
by combinations of the CS and WE controls.
During READ-cycle timing, WE is kept high. Independent of CS, any change in address code causes
new data to be fetched and brought to the output buffer. CS must be low, however, for the output buffer
to be enabled and transfer the data to the output pin.
Address access time, tA, is the time required for an address change to produce new data at the output
pin, assuming CS has enabled the output buffer prior to data arrival. Chip Select-to-output delay,
tCO, is the time required for CS to enable the output buffer and transfer previously fetched data to the
output-pin. Operation with CS continuously held low is permissible.
Writing occurs only during the time both CS and WE are low. Minimum write pulse width, tWP, refers
to this simultaneous low region. Data set-up and hold times are measured with respect to whichever
control first rises. Successive write operations may be performed with CS continuously held low. WE
then is used to terminate WRITE between address changes. Alternatively, WE may be held low for
successive WRITES and CS used for WRITE interruption between address change.
In any event, either WE or CS (or both) must be high during address transitions to prevent erroneous
WRITE.
Unser Halbleiter Katalog (ohne NTE-Sortiment)
NTE Sortiment (unser ganzes Sortiment)
Einzel-Halbleiter (ganzes Sortiment)
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Anmerkung zu den NTE/ECG Austauschhalbleiter:
NTE-Austauschhalbleiter (früher ECG Philips und Sylvania) sind sorgfältig
ausgesuchte und erprobte Halbleiter, die einen sicheren Ersatz
für Originaltypen verschiedenster Hersteller und Ursprünge für
fast alle Applikationsbereiche im Wartungsdienst bieten.
Alle NTE-Austausch-Halbleiter sind einzeln in durchsichtigen
Plastikbeuteln verpackt, auf welchen die wichtigsten Daten
vermerkt sind.